readme - Fast Design



Overview:

This design highlights the Dhrystone MIPS performance of the Nios II/f core. This system achieves over 160 DMIPS on the Nios Development Board, Stratix II Edition, and can achieve over 200 DMIPS when targeting the fastest speed grade of a Stratix II device. This design is provided for the Nios Development Board, Stratix II RoHS-Compliant Edition, Stratix II Edition, Stratix Edition and Stratix Professional Edition. Fast designs targeting the Stratix III and Cyclone III device families are also provided.

Contents of the System:

 - Nios II/f Core w/SPFP
 - JTAG Debug Module (Level 1)
 - On-Chip RAM 98304 Bytes
 - JTAG UART
 - Timer
 - One PLL 200MHz





Supported Software Examples:

 - Blank Project
 - Hello World
 - Dhrystone
 - Hello Free-Standing
 - Hello World Small

Further notes:

- The top level of this design is the HDL file generated by SOPC Builder. 
  Clicking on the top level of the hierarchy allows you to view this HDL or open the SOPC Builder tool.

- This Quartus II project contains assignments that match the port names produced by SOPC Builder. 
  If you add or modify SOPC Builder components, the pin assignments may no longer be valid. 
  To view the Assignment Editor in the Quartus II software, in the Assignments menu, click "Assignment Editor".

- The current version of the Nios II EDS hardware design example uses an HDL file as the top level of the design hierarchy.  
  If you would like to use a schematic-based top level instead (BDF), follow the steps listed below.  
  For more information and details, refer to the Nios II Embedded Design Suite Release Note.

1.)  In the Quartus II software, open the top-level HDL file (.v or .vhd) for the design.
2.)  Create a symbol for the HDL file by clicking "File -> Create/Update -> Create Symbol Files for Current File"
3.)  Create a new BDF file by clicking "File -> New -> Block Diagram/Schematic File."
4.)  Instantiate the symbol in the BDF by double-clicking in the empty space of the BDF file and selecting "Project -> <symbol filename>"
5.)  Instantiate pins in the BDF by double-clicking empty space, then typing "input", "output", or "bidir".
6.)  Rename the pins and connect them to the appropriate ports on the symbol.
7.)  Save the BDF as a unique filename.
8.)  Set the BDF as your top level entity by clicking, "Project -> Set as Top-Level Entity".
9.)  Recompile the Quartus II project.

 - For more information, please refer to http://www.altera.com/support/examples/nios2/exm-nios2.html

